When working with power semiconductor devices, especially power semiconductor devices having a MOSFET control head, as a rule, it takes a certain time until the power semiconductor device (hereinafter also component or element, for short) is completely turned on and the voltage, which drops across the load terminals or power terminals of the device, and in the case of IGBTs, corresponds to the collector-emitter voltage usually denoted by VCE, has fallen to the desired low values. In the event of a fault, e.g., if an IGBT is turned on when there is a short circuit, the resulting output current through the load terminals of the device may become so high that it exceeds the output-current values which the IGBT provides in the linear operating range. In such a case, the output current reaches a saturation value, while the collector-emitter voltage of the IGBT remains at a high level. This results in a very high power loss of the IGBT.
Therefore, there is the need to limit the energy in the power semiconductor device in order to avoid its destruction. To that end, the on-time of the device in the case of a short circuit is typically limited to 10 μs. To monitor the proper operation, typically, what is termed VCE monitoring is used, by which it is possible to recognize whether the output current of the power semiconductor switch is exceeding a current permissible for its proper operation, i.e., the VCE monitoring is used to recognize an overcurrent at the output of the semiconductor switch. During the VCE monitoring, the collector-emitter voltage of the IGBT, i.e., the voltage drop across the IGBT, is measured and compared to a setpoint value (a reference voltage) which the intention is to stay below within the permissible short-circuit duration during proper operation (also called normal operation). During normal operation, after the above-mentioned time of typically 10 μs permissible for the short-circuit operation has passed, the collector-emitter voltage has usually fallen off to a value of less than 10 V. However, depending on the voltage class of the device, its operating conditions, the technology used for the device and the adjustment of the charge-carrier plasma in the device, higher values are also possible and permissible for the collector-emitter voltage such as, for example, collector-emitter voltage values in the range of up to 1000 V for IGBTs of the voltage class 6.5 kV. Here, the collector-emitter voltage typically drops to below 10 V only after a longer ON duration than would be permissible for the short-circuit case.
Several methods for VCE monitoring are known from the related art. Thus, the American patent U.S. Pat. No. 4,423,457 describes a method in which the high voltage occurring at the collector of a transistor is limited by a diode to values which can be processed by the circuit downstream of the device. The cathode of the diode is connected to the collector of the transistor. A current source implemented within a driving circuit for the transistor is connected to the anode of the diode. The diode has a reverse voltage which is higher than the voltage defined by the voltage class of the transistor to be driven. For even higher reverse voltages, a plurality of diodes are connected in series. The potential at the anode of the diode follows the potential of the collector of the transistor plus the forward voltage of the diode until the output voltage of the voltage source connected to the anode is limited to a voltage value made available by the driving circuit. The maximally measurable collector-emitter voltage is thus limited to its supply voltage minus the forward voltage of the diode. With the method described in U.S. Pat. No. 4,423,457, typically collector-emitter voltages of less than 10 V are measurable after the time allowed for the short-circuit operation has elapsed. In principle, this is sufficient for IGBT voltage classes of 600 V to 1700 V.
During the closing operation in normal operation, the VCE monitoring is usually deactivated during a suppression time. The suppression time is set in a simple manner by a capacitor which is connected to the current source. During the OFF state of the transistor, this capacitor is discharged with the aid of a signal-processing unit via a switch, and in response to the closing operation of the transistor, is charged via the current source.
“Universal Chipset for IGBT and Power-MOSFET Gate Drivers” by Jan Thalheim and Heinz Rüedi, PCIM Europe, Nürnberg, 2007, likewise describes a method for VCE monitoring, which is explained in the following with reference to FIG. 1. FIG. 1 shows a circuit configuration 1 having a driving circuit 2 and a power semiconductor switch S with driven gate terminal G (also denoted as gate), that permits VCE monitoring with the aid of a compensated voltage divider. Driving circuit 2 is used to drive power semiconductor switch S. A voltage divider, which is formed by resistors RVCE1, RVCE2, RVCE3 and RME, is used to reduce the high voltage, occurring at power terminal/collector C of power semiconductor switch S in case of a fault, to values which lie within the permissible input-voltage range of comparator COMP of the following/downstream signal-processing unit. In the case of the voltage divider, resistors RVCE1, RVCE2, RVCE3 are connected in series. Typically, the values of resistors RVCE1, RVCE2, RVCE3 must be selected to be very high in order to keep the power loss within these resistors, and thus the costs for the components and cooling measures which may be necessary, as low as possible. Because of these high values for resistors RVCE1, RVCE2, RVCE3, and the parasitic input capacitor CAP of the signal-processing unit or of comparator COMP, (including their wiring), a relatively high time constant or response time results for the circuit configuration, leading to a corresponding signal delay. Furthermore, parasitic input capacitor CAP can fluctuate sharply in terms of value depending on the process. Particularly in the case of a more complex wiring with the aid of a printed circuit board (PCB), parasitic input capacitor CAP may depend strongly on the layer construction, the manufacturer and the production lot.
To reduce this effect, that is, the relatively high time constant caused possibly by parasitic input capacitor CAP, a compensated voltage divider may be used, in which dominant capacitors CVCE1, CVCE2, CVCE3, CME are assigned to resistors RVCE1, RVCE2, RVCE3, RME (see FIG. 1). The disadvantages in so doing are an additionally necessary space requirement, a decrease in the maximally permitted operating temperature, an increased number of components, increased costs and, as a rule, reduced reliability. A further disadvantage in using such a compensated voltage divider is that, given a monolithic integration of comparator COMP and control unit CONTROL of the signal-processing unit, a suppression time, in which the VCE monitoring is deactivated, must be set subsequent to the comparison of the measured collector-emitter voltage to the setpoint value carried out by comparator COMP, thus, must be carried out within or with the aid of control unit CONTROL. However, this requires additional measures for setting the suppression time, such as a digital programming or further connecting pins at the monolithically integrated signal-processing unit.
The indicated disadvantages of the compensated voltage divider may be avoided by not using dominant capacitors for compensating the above-indicated voltage divider RVCE1, RVCE2, RVCE3, RME, but instead, by increasing the input capacitance of the signal-processing unit following power semiconductor switch S, by connecting a (dominant) response-time capacitor CA in parallel to parasitic input capacitor CAP, such that the driving-circuit time constant needed for the realization of the suppression time of the VCE monitoring results. Typically, a response-time resistor RA is assigned to response-time capacitor CA. This is illustrated in FIG. 2, which shows a circuit configuration 1′ having a driving circuit 2′ and a power semiconductor switch S, by which VCE monitoring may be carried out. During the OFF state of power semiconductor switch S, response-time capacitor CA is discharged with the aid of control unit CONTROL via a switch M_D to a lower potential in the form of a predefined reference potential Com or vee of driving circuit 2′. Upon the closing operation of power semiconductor switch S, response-time capacitor CA is then charged via resistor network RVCE1, RVCE2, RVCE3 connected to collector C of power semiconductor switch S. In this context, however, a decrease of the collector-emitter voltage leads to a prolongation of the response time proportional to the decrease. This can lead to an unintentional restriction with respect to the optimal design and operation of power semiconductor switch S, even though the short-circuit energy can be held constant to a great extent in circuit configuration 1′ shown in FIG. 2.
In order to minimize the variation of the response time in a wide range of the collector-emitter voltage, it is suggested in “2SC0435T Description and Application Manual”, CT-Concept Technologie AG, version 24, September 2010, (particularly page 10), available at http://www.igbt-driver.com/fileadmin/Public/PDF/Products/ENG/SCALE2/Cores/2SCO 435T/2SC0435T_Manual.pdf), to limit the potential VCM at the midpoint of the voltage divider, formed by resistors RVCE1, RVCE2, RVCE3, RME, with the aid of a diode DGH (see FIG. 2) to a maximum value VCM_MAX, namely, to an at least partially constant potential, available in driving circuit 2′ for power semiconductor switch S, plus the forward voltage of diode DGH. For small collector-emitter voltages, the voltage divider formed by resistors RVCE1, RVCE2, RVCE3, RME acts in linear fashion. For greater collector-emitter voltages, the output voltage of this voltage divider is limited by diode DGH to the maximum value VCM_MAX. Thus, according to approximation, for collector-emitter voltages which are greater than VCM*RVCE/(RME∥RA), the value for VCM and therefore the response time are constant, RVCE corresponding to the sum of the resistance values of resistors RVCE1, RVCE2, RVCE3, and RME∥RA corresponding to the resistance value of the parallel connection of resistors RME and RA. For example, maximum value VCM_MAX may be derived from operating/supply voltage Viso, or from a voltage, switched into driving circuit 2′ by control unit CONTROL, for gate terminal G of the power semiconductor switch. The switched voltage may be the output voltage at output GH of an output stage M_ON—responsible for the ON state of power semiconductor switch S—of control unit CONTROL. Voltage VCM at the midpoint of voltage divider RVCE1, RVCE2, RVCE3, RME is limited to this maximum value VCM_MAX so long as the collector-emitter voltage is greater than a predefined limiting value VCE_MIN. For collector-emitter voltages which lie below limiting value VCE_MIN, however, the voltage at midpoint VCM of voltage divider RVCE1, RVCE2, RVCE3, RME is less than maximum value VCM_MAX, so that the response time is prolonged accordingly in this case, as well. In general, the driving circuit described in “2SC0435T Description and Application Manual”, CT-Concept Technologie AG, version 24, September 2010 is sufficient for IGBT voltage classes of 600 V to 1700 V.
In principle, the response time of circuit configuration 1′, i.e., of driving circuit 2′, determined by response-time capacitor CA and response-time resistor RA assigned to it (see FIG. 2), should be held constant in a wide range of the collector-emitter voltage. This is achieved by minimizing the quotient or factor VCE_MIN/VCM_MAX of value VCM_MAX defined above and predefined minimum collector-emitter voltage VCE_MIN.
For example, factor VCE_MIN/VCM_MAX may be minimized by increasing the current flowing to midpoint VCM of the resistor network formed by resistors RVCE1, RVCE2, RVCE3, RME, for instance, by reducing the resistance values of resistor network RVCE1, RVCE2, RVCE3 connected to collector C of power semiconductor switch S. However, this measure conflicts with the fact that, as mentioned at the outset, the values of resistors RVCE1, RVCE2, RVCE3 of the resistor network, connected in series to collector C, should be selected to be very high in order to keep the power loss within resistors RVCE1, RVCE2, RVCE3, caused by a high collector-emitter voltage, and therefore the costs for the components and cooling measures which may be necessary, as low as possible.
Alternatively, factor VCE_MIN/VCM_MAX may be minimized by reducing the current flowing away from midpoint VCM of the resistor network formed by resistors RVCE1, RVCE2, RVCE3, RME, for example, by increasing or maximizing the value of response-time resistor RA. In addition, the value of resistor RME of the voltage divider could also be increased. Resistor RME may be omitted in circuit configuration 1′ shown in FIG. 2, since the input voltage for comparator COMP is already limited by diode DGH. However, the result of these measures would be that, in the case of the predefined response time, the value for response-time capacitor CA would have to be reduced accordingly, the result being that the response time would be influenced more strongly by parasitic and process-dependent capacitor CAP. Particularly for a cost-effective, compact design of the circuit configuration having a more complex driving circuit (also called driver), the parasitic effects are typically dominating to such an extent that a production-suitable tuning of the response time of the circuit configuration, above all with regard to process control and thermal stress of the components, can only be realized with difficulty, especially for IGBT voltage classes of 3300 V to 6500V.
The consequence of parasitic effects becomes even more relevant, and therefore the tuning suitable for production is rendered even more difficult, if both the VCE monitoring, i.e., the monitoring of the collector-emitter voltage of power semiconductor switch S described at the outset, and a dynamic so-called active clamping function (opening overvoltage limiting function) are to be realized by the driving circuit. The active clamping function is used to limit an overvoltage possibly occurring when turning power semiconductor switch S off. A circuit configuration 1″ having such a driving circuit 2″ is shown in FIG. 3 (internal knowledge of the Applicant at the date of filing).
By the use of the active clamping function, an overvoltage possibly occurring upon turning off power semiconductor switch S is limited with the aid of series-connected semiconductor devices DZCE0, DZCE1, DZCE2, DZCE3 (for example, Zener diodes, avalanche diodes (see http://de.wikipedia.org/wiki/Avalanchediode) and/or transient-voltage-suppressor diodes (see http://de.wikipedia.org/wiki/Suppressordiode)), which are operated in breakdown when a specific collector-emitter voltage is exceeded, by turning power semiconductor switch S on again, the potential at gate terminal G of power semiconductor switch S being raised for a time approximately to the level of supply voltage Viso.
The effectiveness of the active clamping function can be further improved by reducing the output current of control unit CONTROL available on the gate-terminal line (also called gate line) which leads from control unit CONTROL (also called gate driver) to gate terminal G of power semiconductor switch S. This is achieved by returning a portion of the current of semiconductor devices DZCE0, DZCE1, DZCE2, DZCE3 operated in breakdown, across a resistor RACL to a control input ACL of control unit CONTROL. Control input ACL is preferably a low-impedance input of a current mirror circuit, the output current available at output GL of an output stage M_OFF of control unit CONTROL responsible for the OFF state or opening operation of power semiconductor switch S being reduced as a function of the current flowing into control input ACL.
According to the related art, when working with a dynamic active-clamping function, one semiconductor device DZCE0 of serially-connected semiconductor devices DZCE0, DZCE1, DZCE2, DZCE3 operated in breakdown is bypassed for a certain time during the circuit-breaking operation of power semiconductor switch S. The goal of the dynamic active-clamping function is, on one hand, to increase the sum of the breakdown voltages in the OFF state of power semiconductor switch S, and on the other hand, to reduce the sum of the breakdown voltages during the actual circuit-breaking operation, so that the performance capability of power semiconductor switch S may be better utilized without leaving its safe operating area.
However, in realizing the VCE monitoring and the dynamic active-clamping function in a circuit configuration 1″ or driving circuit 2″ as shown in FIG. 3, the following difficulties are apparent. As mentioned above, one semiconductor device DZCE0, that is, a part of the serially-connected semiconductor devices DZCE0, DZCE1, DZCE2, DZCE3 operated in breakdown in response to the exceedance of a specific collector-emitter voltage, is bypassed for a certain time during the circuit-breaking operation of power semiconductor switch S. The bypass is accomplished by a switch M_DAAC, which is driven by control unit CONTROL via a gate terminal CTRL_DAAC.
However, if switch M_DAAC is closed during a closing operation of power semiconductor switch S, then, because of the change in the voltage drop across M_DAAC, an unintentional charge transfer results between parasitic capacitors CP and response-time capacitor CA. The tuning of the response time or response-time constant, especially the observance of low tolerances of the response time in the case of process fluctuations, is thereby further hampered. In the circuit topology shown in FIG. 3, the minimization of the influence of parasitic capacitors CP, which arises between resistors RVCE1, RVCE2, RVCE3 of the resistor series circuit and the anodes of semiconductor devices DZCE1, DZCE2, DZCE3, would require a relatively complex control of the optimal instant for the change in the switching state of switch M_DAAC, and therefore a complex control unit CONTROL. However, a complex control unit CONTROL also calls for a costly feeding of control unit CONTROL. In particular, it is necessary that control unit CONTROL be designed in such a way that, in response to the exceedance of the breakdown voltages of semiconductor devices DZCE1, DZCE2, DZCE3 during the circuit-breaking operation of power semiconductor switch S, because of an overvoltage occurring at power semiconductor switch S, control unit CONTROL turns power semiconductor switch S on again for a time by raising the potential at gate terminal G of power semiconductor switch S for a time approximately to the level of supply voltage Viso. Thus, control unit CONTROL must be designed to carry out the active clamping function. In addition, at the same time, control unit CONTROL must ensure that switch M_DAAC remains safely closed, so as not to unintentionally increase the nominal value for the permissible overvoltage during the circuit-breaking operation of the power semiconductor switch. For this, it is necessary that the potential at gate terminal CTRL_DAAC of switch M_DAAC be higher than the potential at gate terminal G of power semiconductor switch S, and furthermore, be higher than the level of supply voltage Viso. This usually requires the use of relatively complex “charge-pump” or “bootstrap” feedings. However, because of the high charge at the gate terminal of switch M_DAAC, a relatively high stress of the feeding results, especially when power semiconductor switch S is operated at higher switching rates.